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Integrated Circuit Systems, Inc.
Product Data Sheet
M2025/26
VCSO BASED CLOCK PLL WITH AUTOSWITCH
PIN ASSIGNMENT (9 x 9 mm SMT)
FIN_SEL1 GND P_SEL2 DIF_REF0 nDIF_REF0 REF_SEL DIF_REF1 nDIF_REF1 VCC FIN_SEL0 MR_SEL1 MR_SEL0 LOL NBW VCC DNC DNC DNC 27 26 25 24 23 22 21 20 19
GENERAL DESCRIPTION
The M2025/26 is a VCSO (Voltage Controlled SAW Oscillator) based clock jitter attenuator PLL designed for clock jitter attenuation and frequency translation. The device is ideal for generating the transmit reference clock for optical network systems supporting 2.5-10 GB data rates. It can serve to jitter attenuate a stratum reference clock or a recovered clock in loop timing mode. The M2025/26 module includes a proprietary SAW (surface acoustic wave) delay line as part of the VCSO. This results in a high frequency, high-Q, low phase noise oscillator that assures low intrinsic output jitter.
28 29 30 31 32 33 34 35 36
M2025 M2026
(Top View)
18 17 16 15 14 13 12 11 10
P_SEL1 P_SEL0 nFOUT FOUT GND REF_ACK AUTO VCC GND
FEATURES
Integrated SAW (surface acoustic wave) delay line; low phase jitter of < 0.5ps rms, typical (12kHz to 20MHz or 50kHz to 80MHz) Output frequencies of 15 to 700 MHz * LVPECL clock output (CML and LVDS options available) Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL Loss of Lock (LOL) output pin; Narrow Bandwidth control input (NBW pin) AutoSwitch (AUTO pin) - automatic (non-revertive) reference clock reselection upon clock failure Acknowledge pin (REF_ACK pin) indicates the actively selected reference input Options for Hitless Switching (HS) with or without Phase Build-out (PBO) to enable SONET (GR-253) /SDH (G.813) MTIE and TDEV compliance during reselection Single 3.3V power supply Small 9 x 9 mm SMT (surface mount) package
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations Using M2025-11-622.0800 or M2026-11-622.0800
Input Reference Clock (MHz)
(M2025) (M2026)
GND GND GND OP_IN nOP_OUT nVC VC OP_OUT nOP_IN
1 2 3 4 5 6 7 8 9
PLL Ratio
(Pin Selectable)
(M2025) (M2026)
Output Clock (MHz)
19.44 or 38.88 77.76 155.52 622.08
32 or 16 8 4 1
622.08
Table 1: Example I/O Clock Frequency Combinations
* Specify VCSO center frequency at time of order.
SIMPLIFIED BLOCK DIAGRAM
M2025/26
NBW
MUX PLL Phase Detector
Loop Filter
DIF_REF0 nDIF_REF0 DIF_REF1 nDIF_REF1 REF_ACK REF_SEL AUTO Auto
Ref Sel
0
R Div
(1, 4, 16, 64)
VCSO
1
M Divider
0 1
LOL Phase Detector
Mfin Divider
(1, 4, 8, 32 or 1, 4, 8, 16)
(1, 4, 16, 64)
LOL P Divider
(1, 4, 8, 32 or TriState)
Tri-state
FOUT nFOUT
MR_SEL1:0 FIN_SEL1:0 P_SEL2:0
2 2 3
M / R Divider
LUT
Mfin Divider
LUT
P Divider
LUT
Figure 2: Simplified Block Diagram
M2025/26 Datasheet Rev 1.0
M2025/26 VCSO Based Clock PLL with AutoSwitch
Revised 30Jul2004
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M2025/26
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Product Data Sheet
PIN DESCRIPTIONS
Number 1, 2, 3, 10, 14, 26 4 9 5 8 6 7 11, 19, 33 12 Name GND OP_IN nOP_IN nOP_OUT OP_OUT nVC VC VCC AUTO I/O Configuration Description
Ground Input Output Input Power Input Internal pull-down resistor
1
Power supply ground connections. External loop filter connections. See Figure 5, External Loop Filter, on pg. 8. Power supply connection, connect to +3.3V. Automatic/manual reselection mode for clock input: Logic 1 automatic reselection upon clock failure (non-revertive) Logic 0 manual selection only (using REF_SEL) Reference Acknowledgement pin for input mux state; outputs the currently selected reference input pair. Can also be used to control an external clock switch. Logic 1 indicates nDIF_REF1, DIF_REF1 Logic 0 indicates nDIF_REF0, DIF_REF0 Clock output pair. Differential LVPECL.
13
REF_ACK
Output
15 16 17 18 25 20 21 22 23 24 27 28 29 30 31
FOUT nFOUT P_SEL1 P_SEL0 P_SEL2 nDIF_REF1 DIF_REF1 REF_SEL nDIF_REF0 DIF_REF0 FIN_SEL1 FIN_SEL0 MR_SEL0 MR_SEL1 LOL
Output Input Input Input Input Input Input
No internal terminator
P divider selection. LVCMOS/LVTTL. Internal pull-down resistor1 Post-PLL , 5, P Divider Look-Up Table (LUT), on pg. 3. See Table Biased to Vcc/2 2 Internal pull-down resistor1 Internal pull-down resistor1 Biased to Vcc/2 2 Internal pull-down resistor 1 Reference clock input pair 1. Differential LVPECL or LVDS. Resistor bias on inverting terminal supports TTL or LVCMOS. Reference clock input selection. LVCMOS/LVTTL: Logic 1 selects DIF_REF1, nDIF_REF1. Logic 0 selects DIF_REF0, nDIF_REF0. Reference clock input pair 0. Differential LVPECL or LVDS. Resistor bias on inverting terminal supports TTL or LVCMOS.
Input clock frequency selection. LVCMOS/LVTTL. Internal pull-down resistor1 See Table 3, Mfin Divider Look-Up Table (LUT) on pg. 3. M and R divider value selection. LVCMOS/ LVTTL. Internal pull-UP resistor1 See Table 4, M and R Divider Look-Up Table (LUT) on pg. 3.
Output
32 34, 35, 36
NBW DNC
Input
Internal pull-UP resistor1 Do Not Connect.
Loss of Lock indicator output. Asserted when internal PLL is not tracking the input reference for frequency and phase. 3 Logic 1 indicates loss of lock. Logic 0 indicates locked condition. Narrow Bandwidth enable. LVCMOS/LVTTL: Logic 1 - Narrow loop bandwidth, RIN = 2100k . Logic 0 - Wide bandwidth, RIN = 100k .
Table 2: Pin Descriptions
Note 1: For typical values of internal pull-down and pull-UP resistors, see DC Characteristics on pg. 10. Note 2: Biased toVcc/2, with 50k to Vcc and 50k to ground. See Differential Inputs Biased to VCC/2 on pg. 10. Note 3: See LVCMOS Outputs in DC Characteristics on pg. 10.
M2025/26 Datasheet Rev 1.0 Integrated Circuit Systems, Inc.
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M2025/26
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Product Data Sheet
DETAILED BLOCK DIAGRAM
RLOOP CLOOP RPOST CPOST CPOST RLOOP CLOOP OP_OUT RPOST nOP_OUT nVC VC
External Loop Filter Components
M2025/26
OP_IN
nOP_IN
NBW
MUX PLL Phase Detector
DIF_REF0 nDIF_REF0 DIF_REF1 nDIF_REF1 REF_ACK REF_SEL AUTO
Auto Ref Sel
RIN
0
R Div (1, 4, 16, 64)
RIN
1
M Div (1, 4,16, 64) LOL Phase Detector
Loop Filter Amplifier Mfin Divider (1, 4, 8, 32) or (1, 4, 8, 16)
Phase Locked Loop (PLL)
SAW Delay Line
Phase Shifter
VCSO
0 1
LOL
M / R Divider LUT Mfin Divider LUT P Divider LUT
MR_SEL1:0 FIN_SEL1:0 P_SEL2:0
2 2 3
P Divider (1, 4, 8, 32, TriState)
CML or PECL Options
FOUT nFOUT
Figure 3: Detailed Block Diagram
DIVIDER SELECTION TABLES
Mfin Divider Look-Up Table (LUT) The FIN_SEL1:0 pins select the Mfin divider value, which establishes the PLL clock multiplication ratio. Since the VCSO frequency is fixed, this allows input reference selection.
FIN_SEL1:0
P Divider Look-Up Table (LUT) The P_SEL2:0 pins select the P divider values, which set the output clock frequency. A P divider of value of 1 will provide a 622.08MHz output when using a 622.08MHz VCSO, for example. P divider values of 4, 8, or 32 are also available, plus a TriState mode. The output can be placed into the valid states as listed in Table 5.
P_SEL2:0
Mfin Value
(M2025) (M2026)
Input Ref. Freq. (MHz) 1
M2025-yz-622.0800 or M2026-yz-622.0800
0 0 1 1
0 1 0 1
32 or 16 8 4 1
19.44 or 38.88 77.76 155.52 622.08
P Value for FOUT 32 32 1 4 8 4 8 Tri-state
M2025-yz-622.0800 or M2026-yz-622.0800
Output Frequency (MHz)
FOUT
Table 3: Mfin Divider Look-Up Table (LUT)
Note 1: Example with M2025-yz-622.0800 or M2026-yz-622.0800
M and R Divider Look-Up Table (LUT) The MR_SEL1:0 pins select the M and R divider values, which establish phase detector frequency. A lower phase detector frequency improves jitter tolerance and lowers loop bandwidth.
MR_SEL1:0
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
19.44 19.44 622.08 155.52 77.76 155.52 77.76 N/A
Table 5: P Divider Look-Up Table (LUT)
M 1 4 16 64
R 1 4 16 64
Description
0 0 1 1
0 1 0 1
1
Four sets of divider values to enable adjustment of bandwidth and jitter tolerance
Note 1: Do not use with FIN_SEL1:0=11; Maximum Phase Detector Frequency=175MHz
Table 4: M and R Divider Look-Up Table (LUT)
M2025/26 Datasheet Rev 1.0 Integrated Circuit Systems, Inc.
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General Guidelines for M and R Divider Selection
M2025/26
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Product Data Sheet Input Reference Clocks Two clock reference inputs and a selection mux are provided. Either reference clock input can accept a differential clock signal (such as LVPECL or LVDS) or a single-ended clock input (LVCMOS or LVTTL on the non-inverting input).
A single-ended reference clock on the unselected reference input can cause an increase in output clock jitter. For this reason, differential reference inputs are preferred; interference from a differential input on the non-selected input is minimal.
* A lower phase detector frequency should be used for
loop timing applications to assure PLL tracking, especially during GR-253 jitter tolerance testing. The recommended maximum phase detector frequency for loop timing mode is 19.44MHz. When LOL is to be used for system health monitoring, the phase detector frequency should be 5MHz or greater. Low phase detector frequencies make LOL overly sensitive, and higher phase detector frequencies make LOL less sensitive. The LOL pin should not be used during loop timing mode. The preceding guideline also applies when using the AutoSwitch Mode, since AutoSwitch uses the LOL output for clock fault detection.
*
*
FUNCTIONAL DESCRIPTION
The M2025/26 is a PLL (Phase Locked Loop) based clock generator that generates output clocks synchronized to one of two selectable input reference clocks. An internal high "Q" SAW delay line provides low jitter signal performance and establishes the output frequency of the VCSO (Voltage Controlled SAW Oscillator). In a given M2025/26 device, the VCSO center frequency is fixed. A common center frequency is 622.08MHz, for SONET for SDH optical network applications. The VCSO center frequency is specified at time of order (see "Ordering Information" on pg. 12). The VCSO has a guaranteed tuning range of 120 ppm (commercial temperature grade). Pin selectable dividers are used within the PLL and for the output clock. This enables tailoring of device functionality and performance. The Mfin divider controls the overall PLL multiplication ratio and thus determines the input reference clock (see Table 3, on pg. 3). The M and R dividers control the phase detector frequency (see Table 4). The P divider scales the VCSO output enabling lower output frequency selections (Table 5). The M2025/26 includes a Loss of Lock (LOL) indicator, which provides status information to system management software. A Narrow Bandwidth (NBW) control pin is provided as an additional mechanism for adjusting PLL loop bandwidth without affecting the phase detector frequency. Options are available for Hitless Switching (HS) with or without Phase Build-out (PBO). They provide SONET/SDH MTIE and TDEV compliance during a reference clock reselection. Allowance for a single-ended input has been facilitated by a unique input resistor bias scheme, which is described next and shown in Figure 4.
M2025/26 Datasheet Rev 1.0 Integrated Circuit Systems, Inc.
Configuration of a single-ended input has been facilitated by biasing nDIF_REF0 and nDEF_REF1 to Vcc/2, with 50k to Vcc and 50k to ground. The input clock structure, and how it is used with either LVCMOS/LVTTL inputs or a DC- coupled LVPECL clock, is shown in Figure 4.
DIF_REF0
50k VCC 50k X 50k MUX
LVCMOS/ LVTTL
nDIF_REF0
VCC
0
DIF_REF1
LVPECL
127 VCC 127 VCC 50k
1
82
50k
nDIF_REF1 REF_SEL
82
50k
M2025/26
Figure 4: Input Reference Clocks
Differential Inputs
Differential LVPECL inputs are connected to both reference input pins in the usual manner. The external load termination resistors shown in Figure 4 (the 127 and 82 resistors) is ideally suited for both AC and DC coupled LVPECL reference clock lines. These provide the 50 load termination and the VTT bias voltage.
Single-ended Inputs
Single-ended inputs (LVCMOS or LVTTL) are connected to the non-inverting reference input pin (DIF_REF0 or DIF_REF1). The inverting reference input pin (nDIF_REF0 or nDIF_REF1) must be left unconnected.
In single-ended operation, when the unused inverting input pin (nDIF_REF0 or nDEF_REF1) is left floating (not connected), the input will self-bias at VCC/2.
PLL Operation The M2025/26 is a complete clock PLL. It uses a phase detector and configurable dividers to synchronize the output of the VCSO with the selected reference clock.
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The M2025/26 components are similar to the M2020/21 components except that the M2025/26 includes the selectable AutoSwitch feature. The M2025/26 also has only one clock output, as the AutoSwitch control pins replace of the second output. The PLL will work correctly, meaning it will phase-lock the VCSO output to the input reference clock, when the internal phase detector inputs are able to run at the same frequency. This means the PLL dividers must be set appropriately and a suitable reference frequency must be chosen for the intended output frequency. When the PLL is not set up appropriately, the VCSO is forced to its upper or lower operating limit which is typically about 250 ppm above or below the VCSO center frequency (no more than 500 ppm above or below). In normal phase-locked condition, the instantaneous phase error is measured by the phase detector and is converted to charge pump current pulses. These current pulses are then integrated by the external loop filter to create a VCSO control voltage. The loop filter acts as a low pass filter to remove unwanted reference clock jitter above a determined frequency or PLL bandwidth. For reference phase jitter frequencies within the loop bandwidth, phase jitter amplitude is passed on to the output clock according to the PLL loop frequency response curve. The relationship between the nominal VCSO center frequency (Fvcso), the M divider, and the input reference frequency (Fin) is: Fvcso = Fin x Mfin x --R
Example Frequency and Divider Combinations Using M2026-yz-622.0800 Fvcso = Fin 38.88 77.76 155.52 622.08 x Mfin x M/R 16 x (1/1, 4/4, etc.) 8 x (1/1, 4/4, etc.) 4 x (1/1, 4/4, etc.) 1 x (1/1, 4/4, etc.) M
M2025/26
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Product Data Sheet The P_SEL2:0 pins select the value for the P divider. (See Table 5 on pg. 3.) Accounting for the P divider, the complete relationship between the input clock reference frequency (Fin) and output clock frequency (Fout) is defined as: M x Mfin Fvcso Fout = ------------------- = Fin x ------------------------Due to the narrow tuning range of the VCSO (+120ppm guaranteed), appropriate selection of all of the following are required for the PLL be able to lock: VCSO center frequency, input frequency, and divider selections. TriState The TriState feature puts the LVPECL output driver into a high impedance state, effectively disconnecting the driver from the FOUT and nFOUT pins of the device. A logic 0 is then present on the clock net. The impedance of the clock net is then set to 50 by the external circuit resistors. (This is in distinction to a CMOS output in TriState, in which case the net goes to a high impedance and the logic value floats.) The 50 impedance level of the LVPECL TriState allows manufacturing In-circuit Test to drive the clock net with an external 50 generator to validate the integrity of clock net and the clock load.
Any unused output (single-ended or differential) should be left unconnected (floating) in system application. This minimizes output switching current and therefore minimizes noise modulation of the VCSO. P Rx P
622.08
Loss of Lock Indicator (LOL) Output Pin Under normal device operation, when the PLL is locked, the LOL Phase Detector drives LOL to logic 0. Under circumstances when the VCSO cannot fully phase lock to the input (as measured by a greater than 4 ns discrepancy between the feedback and reference clock rising edges at the LOL Phase Detector) the LOL output goes to logic 1. The LOL pin will return back to logic 0 when the phase detector error is less than 2 ns. The loss of lock indicator is a low current LVCMOS output.
Guidelines for Using LOL
Table 6: Example I/O Clock Frequency Combinations
The M, R, and Mfin dividers can be set by pin configuration using the input pins MR_SEL1, MR_SEL0, FIN_SEL1, and
FIN_SEL0.
Post-PLL Divider The M2025/26 also features a post-PLL (P) divider. Through use of the P divider, the device's output frequency (Fout) can be that of the VCSO (such as 622.08MHz) or the VCSO frequency divided by 4, 8 or 32 (common optical reference clocks in SONET and SDH systems).
M2025/26 Datasheet Rev 1.0 Integrated Circuit Systems, Inc.
In a given application, the magnitude of peak-to-peak jitter at the phase detector will usually increase as the R divider is increased. If the LOL pin will be used to detect an unusual clock condition, or a clock fault, the MR_SEL1:0 pins should be set to provide a phase detector frequency of 5MHz or greater (the phase detector frequency is equal to Fin divided by the R divider). Otherwise, false LOL indications may result. A phase detector frequency of 10MHz or greater is desirable when reference jitter is over 500ps, or when the device is used within a noisy system environment. LOL should not be used when the device is used in a loop timing application.
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AutoSwitch (AUTO) Reference Clock Reselection This device offers an automatic reference clock reselection feature for switching input reference clocks upon a reference clock failure. With the AUTO input pin set to high and the LOL output low, the device is placed into automatic reselection (AutoSwitch) mode. Once in AutoSwitch mode, when LOL then goes high (due to a reference clock fault), the input clock reference is automatically reselected internally, as indicated by the state change of the REF_ACK output. Automatic clock reselection is made only once (it is non-revertive). Re-arming of automatic mode requires placing the device into manual selection (Manual Select) mode (AUTO pin low) before returning to AutoSwitch mode (AUTO pin high).
Using the AutoSwitch Feature See alsoTable 7, Example AutoSwitch Sequence.
M2025/26
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Product Data Sheet
REF_ACK output always indicates the reference selection status and the LOL output always indicates the PLL lock
status. A successful automatic reselection is indicated by a change of state of the REF_ACK output and a momentary level high of the LOL output (minimum high time is 10 ns).
If an automatic reselection is made to a non-valid reference clock (one to which the PLL cannot lock), the REF_ACK output will change state but the LOL output will remain high.
No further automatic reselection is made; only one reselection is made each time the AutoSwitch mode is armed. AutoSwitch mode is re-armed by placing the device into Manual Select mode (AUTO pin low) and then into AutoSwitch mode again (AUTO pin high). Following an automatic reselection and prior to selecting Manual Select mode (AUTO pin low), the REF_SEL pin has no control of reference selection. To prevent an unintential reference reselection, AutoSwitch mode must not be re-enabled until the desired state of the REF_SEL pin is set and the LOL output is low. It is recommended to delay the re-arming of AutoSwitch mode, following an automatic reselection, to ensure the PLL is fully locked on the new reference. In most system configurations, where loop bandwidth is in the range of 100-1000 Hz and damping factor below 10, a delay of 500 ms should be sufficient. Until the PLL is fully locked intermittent LOL pulses may occur.
In application, the system is powered up with the device in Manual Select mode (AUTO pin is set low), allowing sufficient time for the reference clock and device PLL to settle. The REF_SEL input selects the reference clock to be used in Manual Select mode and the initial reference clock used in AutoSwitch mode. The REF_SEL input state must be maintained when switching to AutoSwitch mode (AUTO pin high) and must still be maintained until a reference fault occurs. Once a reference fault occurs, the LOL output goes high and the input reference is automatically reselected. The
Example AutoSwitch Sequence
0 = Low; 1 = High. Example with REF_SEL initially set to 0 (i.e., DIF_REF0 selected)
REF_SEL Selected REF_ACK AUTO LOL Conditions
Input
Clock Input DIF_REF0 DIF_REF0 DIF_REF0
Output
Input
Output
Initialization
0 0 0 0 0 0 0 -11 1
0 0 0 0 0 -11 1 1 1
0 0 -11 1 1 1 1 -0-1-
1 -00 0 -11 -00 0 0
Device power-up. Manual Select mode. DIF_REF0 input selected reference, not yet locked to.
LOL to 0: Device locked to reference (may get intermittent LOL pulses until fully locked). AUTO set to 1: Device placed in AutoSwitch mode (with DIF_REF0 as initial reference clock).
Operation & Activation
DIF_REF0 DIF_REF0 -DIF_REF1DIF_REF1 DIF_REF1 DIF_REF1 DIF_REF1
Normal operation with AutoSwitch mode armed, with DIF_REF0 as initial reference clock.
LOL to 1: Clock fault on DIF_REF0, loss of lock indicated by LOL pin, ... ... and immediate automatic reselection to DIF_REF1 (indicated by REF_ACK pin). LOL to 0: Device locks to DIF_REF1 (assuming valid clock on DIF_REF1).
Re-initialization
REF_SEL set to 1: Prepares for Manual Selection of DIF_REF1 before then re-arming AutoSwitch. AUTO set to 0: Manual Select mode entered briefly, manually selecting DIF_REF1 as reference. AUTO set to 1: Device is placed in AutoSwitch mode (delay recommended to ensure device fully locked), re-initializing AutoSwitch with DIF_REF1 now specified as the initial reference clock.
Table 7: Example AutoSwitch Sequence
M2025/26 Datasheet Rev 1.0 Integrated Circuit Systems, Inc.
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Optional Hitless Switching and Phase Build-out The M2025/26 is available with a Hitless Switching feature that is enabled during device manufacturing. In addition, a Phase Build-out feature is also offered. These features are offered as device options and are specified by device order code. Refer to "Ordering Information" on pg. 12. The Hitless Switching feature (with or without Phase Build-out) is designed for applications where switching occurs between two stable system reference clocks. It should not be used in loop timing applications, or when reference clock jitter is greater than 1 ns pk-pk. The Hitless Switching sequence is triggered by the LOL circuit, which is activated by a 4 ns phase transient. This magnitude of phase transient can generated by the CDR (Clock & Data Recovery unit) in loop timing mode, especially during a system jitter tolerance test. It can also be generated by some types of Stratum clock DPLLs (digital PLL), especially those that do not include a post de-jitter APLL (analog PLL). When the M2025/26 is operating in wide bandwidth mode (NBW=0), the optional Hitless Switching function puts the device into narrow bandwidth mode during the Hitless Switching sequence. This allows the PLL to lock the new input clock phase gradually. With proper configuration of the external loop filter, the output clock phase change complies with MTIE and TDEV specifications for GR-253 (SONET) and ITU G.813 (SDH) during input reference clock changes. The optional proprietary Phase Build-out (PBO) function enables the PLL to absorb most of the phase change of the input clock during reference switching. The PBO function selects a new VCSO clock edge for the PLL Phase Detector feedback clock, selecting the edge closest in phase to the new input clock phase. This reduces re-lock time, the generation of wander, and extra output clock cycles. The Hitless Switching and Phase Build-out functions are triggered by the LOL circuit. For proper operation, a low phase detector frequency must be avoided. See "Guidelines for Using LOL" on pg. 5 for information regarding the phase detector frequency.
HS/PBO Sequence Trigger Mechanism
M2025/26
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Product Data Sheet
HS/PBO Operation
Once triggered, the following HS/PBO sequence occurs: 1. The HS function disables the PLL Phase Detector and puts the device into NBW (narrow bandwidth) mode. The internal resistor Rin is changed to 2100k . See the Narrow Bandwidth (NBW) Control Pin on pg. 7. 2. If included, the PBO function adds to (builds out) the phase in the clock feedback path (in VCSO clock cycle increments) to align the feedback clock with the (new) reference clock input phase. 3. The PLL Phase Detector is enabled, allowing the PLL to re-lock. 4. Once the PLL Phase Detector feedback and input clocks are locked to within 2 nsec for 8 consecutive cycles, a timer (WBW timer) for resuming wide bandwidth (in 175 nsec) is started. 5. When the WBW timer times out, the device reverts to wide loop bandwidth mode (i.e., Rin is returned to 100k) and the HS function is re-armed. The LOL pin will indicate lock status on a cycle-to-cycle basis and may be intermittent until PLL phase lock has fully stabilized. Narrow Bandwidth (NBW) Control Pin A Narrow Loop Bandwidth control pin (NBW pin) is included to enable adjustment of the PLL loop bandwidth. In wide bandwidth mode (NBW=0), the internal resistor Rin is 100k . With the NBW pin asserted (NBW=1), the internal resistor Rin is changed to 2100k . This lowers the loop bandwidth by a factor of about 21 (2100 / 100) and lowers the damping factor by about 4.6 (the square root of 21), assuming the same external loop filter component values.
The HS function (or the combined HS/PBO function) is armed after the device locks to the input clock reference. Once armed, HS is triggered by the occurance of a Loss of Lock condition. This would typically occur as a consequence of a clock reference failure, a clock failure upstream to the M2025/26, or a M2025/26 clock reference mux reselection.
M2025/26 Datasheet Rev 1.0 Integrated Circuit Systems, Inc.
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External Loop Filter To provide stable PLL operation, the M2025/26 requires the use of an external loop filter. This is provided via the provided filter pins (see Figure 5). The loop filter is implemented as a differential circuit to minimize system noise interference.
RLOOP CLOOP RPOST CPOST CPOST RLOOP OP_IN
4 9
M2025/26
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Product Data Sheet PLL bandwidth is affected by loop filter component values, "M" and "Mfin" values, and the "PLL Loop Constants" listed in AC Characteristics on pg. 11. The MR_SEL1 and MR_SEL0 settings can be used to actively change PLL loop bandwidth in a given application. See "M and R Divider Look-Up Table (LUT)" on pg. 3. See Table 8, Example Values for Loop Filter External Components, below. PLL Simulator Tool Available A free PC software utility is available on the ICS website (www.icst.com). The M2000 Timing Modules PLL VC Simulator is a downloadable application that simulates 7 PLL jitter and wander transfer characteristics. This enables the user to set appropriate external loop component values in a given application.
CLOOP OP_OUT
8 5
RPOST nOP_OUT nVC
6
nOP_IN
Figure 5: External Loop Filter
Example Values for Loop Filter External Components 1 for M2025-yz-622.0800 and M2026-yz-622.0800
VCSO Parameters: KVCO = 800kHz/V, RIN = 100k (pin NBW = 0), VCSO Bandwidth = 700kHz. Purpose Device Configuration FVCSO FIN_SEL MRSEL 1:0 1:0 (MHz) (MHz) Example External Component Values Nominal Performance With These Values
FRef
R loop 11.5k 23.2k 11.5k 23.2k 5.6k 8.2k 12.0k 8.2k
C loop 2.2F 1.0F 2.2F 1.0F 10F 10F 10F 10F
R post 32.4k 32.4k 32.4k 32.4k 68k 100k 100k 100k
C post PLL Loop Damping Passband Bandwidth Factor Peaking (dB) 470p 470p 470p 470p 470p 470p 470p 470p 1kHz 1kHz 1kHz 1kHz 500Hz 360Hz 260Hz 360Hz 6.0 6.5 6.7 6.5 6.3 6.5 6.7 6.5 0.05 0.06 0.05 0.06 0.05 0.05 0.05 0.05
Frequency Translation, General Usage
155.52 77.76 38.88 2 19.44 622.08
3
622.08 1 0 622.08 0 1 622.08 0 0 622.08 1 1 622.08 0 1 622.08 0 0
01
01 622.08 0 0 2 0 0
3
00 10
Jitter Attenuation, 77.76 Narrow 38.88 2 Bandwidth
01 622.08 0 0 2 0 1
3
19.44
3
00
Table 8: Example Values for Loop Filter External Components
Note 1: KVCO , VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor, and Passband Peaking. For PLL Simulator software, go to www.icst.com. Note 2: M2026 only. Note 3: M2025 only.
Refer to the M2025/26 product web page at www.icst.com/products/summary/m2025-2026.htm additional product information.
M2025/26 Datasheet Rev 1.0 Integrated Circuit Systems, Inc.
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Integrated Circuit Systems, Inc.
M2025/26
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Product Data Sheet
ABSOLUTE MAXIMUM RATINGS1
Symbol Parameter Rating Unit
VI VO VCC TS
Inputs Outputs Power Supply Voltage Storage Temperature
-0.5 to VCC +0.5 -0.5 to VCC +0.5
4.6
V V V
oC
-45 to +100
Table 9: Absolute Maximum Ratings
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
RECOMMENDED CONDITIONS OF OPERATION
Symbol Parameter Min 3.135 Typ 3.3 Max 3.465 Unit
VCC TA
Positive Supply Voltage Ambient Operating Temperature Commercial Industrial
V
oC oC
0 -40
+70 +85
Table 10: Recommended Conditions of Operation
M2025/26 Datasheet Rev 1.0 Integrated Circuit Systems, Inc.
9 of 12 Networking & Communications
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Integrated Circuit Systems, Inc.
M2025/26
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Product Data Sheet
ELECTRICAL SPECIFICATIONS
DC Characteristics
Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT = 622-675MHz, LVPECL outputs terminated with 50 to VCC - 2V
Symbol Parameter
Min 3.135
Typ 3.3 175
Max 3.465 225
Unit Conditions
Power Supply VCC ICC All Differential Inputs Differential Inputs with Pull-down Differential Inputs Biased to VCC/2 1 All LVCMOS / LVTTL Inputs LVCMOS / LVTTL Inputs with Pull-down LVCMOS / LVTTL Inputs with Pull-UP Differential Output VP-P VCMR CIN IIH IIL IIH IIL Rbias VIH VIL CIN IIH
Positive Supply Voltage Power Supply Current Peak to Peak Input Voltage Common Mode Input Input Capacitance Input High Current (Pull-down) Input Low Current (Pull-down) Input High Current (Biased) Biased to Vcc/2 1 Input High Voltage Input Low Voltage Input Capacitance Input High Current (Pull-down)
AUTO, REF_SEL, FIN_SEL1, FIN_SEL0, MR_SEL1, MR_SEL0, P_SEL2, P_SEL1, P_SEL0, NBW
1
V mA V
0.15 DIF_REF0, nDIF_REF0, DIF_REF1, nDIF_REF1 0.5
Vcc - .85 V 4
pF A A k
VCC = VIN = 3.456V
150
DIF_REF0, DIF_REF1
-5
50 150
Rpulldown Internal Pull-down Resistance Input Low Current (Biased) 1
nDIF_REF0, nDIF_REF1
A A k
-150
(Note 1) 2
VIN = 0 to 3.456V
Vcc + 0.3 V 0.8 4
-0.3
V pF A A k
VCC = VIN = 3.456V
AUTO, REF_SEL, FIN_SEL1, FIN_SEL0, MR_SEL1, IIL Input Low Current (Pull-down) MR_SEL0, P_SEL2, P_SEL1, Rpulldown Internal Pull-down Resistance P_SEL0
150 -5
50
IIH IIL Rpullup VOH VOL VP-P VOH VOL
Input High Current (Pull-UP) Input Low Current (Pull-UP) Internal Pull-UP Resistance Output High Voltage Output Low Voltage Peak to Peak Output Voltage 2 Output High Voltage Output Low Voltage
LOL, REF_ACK GND FOUT, nFOUT Vcc - 1.4 Vcc - 2.0 0.4 2.4 NBW
5 -150
50
A A k
VCC = 3.456V VIN = 0 V
Vcc - 1.0 V Vcc - 1.7 V 0.85
V V V IOH= 1mA IOL= 1mA
LVCMOS Outputs
VCC
0.4
Note 1: Biased to Vcc/2, with 50k to Vcc and 50k to ground. See Figure 4, Input Reference Clocks, on pg. 4 Table 11: DC Characteristics Note 2: Single-ended measurement. See Figure 6, Output Rise and Fall Time, on pg. 11.
M2025/26 Datasheet Rev 1.0 Integrated Circuit Systems, Inc.
10 of 12 Networking & Communications
Revised 30Jul2004 w w w. i c s t . c o m
tel (508) 852-5400
Integrated Circuit Systems, Inc.
M2025/26
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Product Data Sheet
ELECTRICAL SPECIFICATIONS (CONTINUED)
AC Characteristics
Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT = 622-675MHz, LVPECL outputs terminated with 50 to VCC - 2V
Symbol Parameter
Min DIF_REF0, nDIF_REF0, DIF_REF1, nDIF_REF1 FOUT, nFOUT Commercial Industrial 10 15
Typ
Max 700 700
Unit Conditions
FIN FOUT APR KVCO PLL Loop Constants 1 RIN
Input Frequency Output Frequency VCSO Absolute Pull-Range VCO Gain Internal Loop Resistor
MHz MHz ppm ppm kHz/V k k kHz dBc/Hz dBc/Hz dBc/Hz ps ps % % ps ps
Fin=19.44 or 38.88 MHz Mfin=32 or 16, M=1, R=1
120 50
200 150
800 100 2100 700
Wide Bandwidth Narrow Bandwidth
BWVCSO VCSO Bandwidth n Phase Noise and Jitter J(t) odc tR tF Single Side Band Phase Noise @622.08MHz Jitter (rms) @622.08MHz Output Duty Cycle 2 Output Rise Time 2 for FOUT, nFOUT Output Fall Time 2 for FOUT, nFOUT
1kHz Offset 10kHz Offset 100kHz Offset 12kHz to 20MHz 50kHz to 80MHz
P = 4, 8, or 32 P=1
-73 -103 -126
0.25 0.25 45 40 200 200 50 50 450 450 0.5 0.5 55 60 500 500
20% to 80% 20% to 80%
Table 12: AC Characteristics
Note 1: Parameters needed for PLL Simulator software; see Table 8, Example Values for Loop Filter External Components, on pg. 8. Note 2: See Parameter Measurement Information on pg. 11.
PARAMETER MEASUREMENT INFORMATION
Output Rise and Fall Time Output Duty Cycle
nFOUT FOUT VP-P Clock Output 20% tR 20% tF odc = tPW tPERIOD tPW (Output Pulse Width) tPERIOD
80%
80%
Figure 6: Output Rise and Fall Time
Figure 7: Output Duty Cycle
M2025/26 Datasheet Rev 1.0 Integrated Circuit Systems, Inc.
11 of 12 Networking & Communications
Revised 30Jul2004 w w w. i c s t . c o m
tel (508) 852-5400
Integrated Circuit Systems, Inc.
Product Data Sheet
M2025/26
VCSO BASED CLOCK PLL WITH AUTOSWITCH
DEVICE PACKAGE - 9 x 9mm CERAMIC LEADLESS CHIP CARRIER
Mechanical Dimensions:
Refer to the M2025/26 product web page at www.icst.com/products/summary/m2025-2026.htm for recommended PCB footprint, solder mask, furnace profile, and related information.
Figure 8: Device Package - 9 x 9mm Ceramic Leadless Chip Carrier
ORDERING INFORMATION
Part Numbering Scheme Part Number:
Standard VCSO Output Frequencies (MHz)* 622.0800 669.3120 625.0000 627.3296 644.5313 666.5143 669.1281 669.3266 670.8386 672.1600 690.5692 669.3120
M202x- 1z - xxx.xxxx
Frequency Input Divider Option 5 = Mfin Divider selections of: 32, 8, 4, or 1 6 = Mfin Divider selections of: 16, 8, 4, or 1 Output type 1 = LVPECL (For CML or LVDS clock output, consult factory) Hitless Switching / Phase Build-out Options 1 = none 2 = Hitless Switching 3 = Hitless Switching with Phase Build-out Temperature " - " = 0 to +70 oC (commercial) I = - 40 to +85 oC (industrial) VCSO Frequency (MHz) See Table 13, right. Consult ICS for other frequencies.
Table 13: Standard VCSO Output Frequencies
Figure 9: Part Numbering Scheme
Note *: Fout can equal Fvcso divided by: 1, 4, 8, or 32
Consult ICS for the availability of other VCSO frequencies.
Example Part Numbers
VCSO Frequency (MHz) Temperature 622.08 625.00
commercial industrial commercial industrial
Order Part Number M2025 - 11 - 622.0800 or M2026- 11 - 622.0800 M2025 - 11I 622.0800 or M2026- 11I 622.0800 M2025 - 11 - 625.0000 or M2026 - 11 - 625.0000 M2025 - 11I 625.0000 or M2026- 11I 625.0000
Table 14: Example Part Numbers
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. M2025/26 Datasheet Rev 1.0 Integrated Circuit Systems, Inc.
12 of 12 Networking & Communications
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